This invention relates to communication control technology, and more particularly to a technique which is especially effective when applied to the serial communication between microprocessors. By way of example, the technique is effectively utilized for a serial communication device having a DMA (direct memory access) controller which transfers transmission data and reception data between a memory of first-in first-out scheme (hereinbelow, termed "FIFO") and a memory of random access scheme.
Heretofore, an LSI for communication such as .mu.PD7201A manufactured by Nippon Electric Company has been provided in order to realize a serial communication between microprocessors. FIG. 4 shows an example of a system which uses this communication LSI .mu.PD7201A. Along with a memory MEM, a DMA controller DMAC and the LSI for serial communication SIO are connected to a microprocessor CPU through a system bus BUS.
In this system, in a case where the microprocessor CPU has data to be transmitted to another microprocessor not shown, it sends a command to the DMA controller DMAC. Then, the DMA controller DMAC delivers addresses onto the system bus BUS and reads out the desired transmission data items in the memory MEM so as to supply them to the communication LSI SIO. The transmission data items supplied to the communication LSI SIO are once stored in a FIFO built therein and are thereafter converted into serial data items, which are output.
On the other hand, when reception data items enter the communication LSI SIO from outside, they are converted into parallel data items every byte, and the parallel data items are stored in a receiving FIFO. When the FIFO is filled up, the communication LSI SIO applies an interrupt to the microprocessor CPU to inform it of the situation. Then, the microprocessor CPU sends a read command to the DMA controller DMAC, and the DMA controller DMAC transfers the receipt data in the FIFO to the memory MEM. Thereafter, the microprocessor CPU accesses the memory MEM, whereby the receipt data can be obtained (refer to "Users Manual of NEC Electron Device .mu.PD7201A", pp. 1-5 and 24-26, issued by Nippon Electric Company in 1984).
The communication LSI .mu.PD7201A is an LSI which performs a control conforming to an HDLC (high-level data link control) protocol that transmits data in a unit called "frame". With the protocol which carries out the data communication in frame unit, it is sometimes desired that the microprocessor executes the analysis of receipt data, etc. every received frame. In this regard, the above system employing the communication LSI .mu.PD7201A is so constructed that, each time final data indicating the end of one frame enters, an interrupt signal is sent to the microprocessor.
However, with the system wherein the microprocessor is interrupted every frame as stated above, when the interrupt shifts a bus mastership to the microprocessor which accordingly executes the process, the transfer of data to the memory MEM by the DMA controller is suspended meantime. As a result, the transfer of the next frame received in the FIFO to the memory MEM becomes impossible, and this forms a cause for lowering the efficiency of communication in the case where a plurality of frames are succesively transmitted to arrive.